`timescale 1ns / 1ps

module branchcomp (
  input  wire [2:0] bralu_op,
  input  [63:0] rs1,
  input  [63:0] rs2,
  input mem_stall,
  output wire br_taken
);

  reg t;
  assign br_taken = t & ~mem_stall;

  always @(*) begin
      case (bralu_op)
        3'b001:begin         //EQ
            if(rs1==rs2) t = 1;
            else t = 0;
        end
        3'b010:begin         //NE
            if(rs1!=rs2) t = 1;
            else t = 0;
        end
        3'b011:begin         //LT
            if($signed(rs1)<$signed(rs2)) t = 1;
            else t = 0;
        end
        3'b100:begin         //GE
            if($signed(rs1)>=$signed(rs2)) t = 1;
            else t = 0;
        end
        3'b101:begin         //LTU
            if(rs1<rs2) t = 1;
            else t = 0;
        end
        3'b110:begin         //GEU 
            if(rs1>=rs2) t = 1;
            else t = 0;
        end
        default:begin
            t=1;
        end
      endcase
  end

endmodule